1. Field of the Invention
The present invention relates to a discrete wavelet transform apparatus for a lattice structure, and in particular to a discrete wavelet transform apparatus for a lattice structure which is capable of implementing a scalable discrete wavelet transform(DWT) of a lattice structure in which the number of registers used for a resolution level has a linearity with respect to the resolution level.
2. Description of the Background Art
Generally, a discrete wavelet transform(DWT) which is known as a tree structure subband analysis is directed to a hierarchical signal transform method. Each state forming a discrete wavelet transform(DWT) filters a low band component and high band component from a signal. The sampling ratio is decreased by 2 at each stage for thereby implementing a filtering operation.
The discrete wavelet transform(DWT) is used in various fields. For example, the DWT may be used for transferring a video image to a receiver side or compressing the same and may be used for an audio signal transmission. In the case of using the DWT for a video coding application, it is possible to prevent a resolution decrease at a boundary portion between blocks.
In order to use the discrete wavelet transform(DWT) in real time, a VLSI is required. Various methods are disclosed for implementing the VLSI. These methods will be explained as follows.
FIG. 1 illustrates an example for performing a DWT based on a quadrature symmetrical filter(QMF) of a 3-level(or 3-stage) tree structure. As shown therein, the 3-level signal processing system includes a signal transfer unit 11 having an analysis quadrature symmetrical filter(QMF) of FIG. 1A, and a signal receiving unit 12 having a synthesis quadrature symmetrical filter(QMF).
The signals are generally analyzed into narrow band signals, for this, an input signal u(n) is analyzed into a low band component by a low band pass digital filter 14 having a high band component and transfer function H(z) based on a high band pass digital filter 13 having a transfer function G(z) at a level 1. The filtered signal, namely, the discrete time signal filtered by the digital filter is down-sampled by xc2xd. Namely, one of two sample values is removed from the filtered discrete time signal. At the levels 2 and 3, the above-described operation is repeated, so that an original signal is divided into a predetermined number of sub-band components. The signal is recovered to the original signal by the low band and high band combining filters 15 and 16 having transfer functions Gxe2x80x2(z) and Hxe2x80x2(z) of each level in the combining quadrature symmetrical filter(QMF) of the signal receiving unit 12. At this time, the sampling ratio is up-sampled by 2 times, and the signal is filtered.
As shown therein, four filters G(z), H(z), Gxe2x80x2(z) and Hxe2x80x2(z) have a perfect reconstruction property, and the filter banks which form each level are same and are duplicated. The number of samples which are computer for each sample is limited to maximum 2 irrespective of the number of levels based on the facts that the filtering speed is decreased at each level. This means that various level computations may be performed using one perfect reconstruction filter bank.
Generally, in order to implement a discrete wavelet transform(DWT) based on an integrated circuit, the discrete wavelet transform is classified into a direct type discrete wavelet transform(DWT) based on the type of a reconstruction filter bank and a discrete wavelet transform(DWT) using a lattice structure.
FIG. 2 illustrates an example for implementing a 3-level(resolution level exceeds 3) discrete wavelet transform(DWT) of a direct type. In particular, the length of the filter is 4. Compared to the example of FIG. 1, the high band pass digital filter 13 and the low band pass digital filter 14 are shown with respect to the signal transmission unit 11. In FIG. 2, reference numeral 17 represent a delay device of a word unit or a register. In addition, in the drawing, xe2x80x9c/xe2x80x9d represents a discrete time.
The digital filters 13 and 14 each include four FIR filter coefficients and g0xe2x88x923(n) and h-3(n) and are formed of four multipliers and four adders. The register stores an output of the current level based on a certain computation sequence, and uses when computing the next level. The construction of FIG. 2 illustrates one example and is directed to a structure formed by a design method capable of minimizing the number of registers.
The construction of FIG. 1 may be implemented in detail. However, if the resolution level and the length of the filter are changed, the construction is reformed. In this case, it is difficult to re-design the construction. In order to overcome the above-described problem, a more adaptive design method is disclosed as shown in FIG. 3. In this example, a routing network 18 is used. The routing network 18 is implemented by a register array or a memory and address generation unit(AGU). Even when the number of registers is greater than the example of FIG. 2, a scalable characteristic is provided with respect to any variation in the resolution level and the length of the filter.
As described above, when implementing a discrete wavelet transform(DWT), the discrete wavelet of the following lattice structure is provided except for adapting the direct type. The above-described example is shown in FIG. 4. As shown in FIGS. 2 and 3, the examples that the level is 3 and the length of the filter is 4 are implemented by the lattice structure. In this structure, since two lattices 19 and 20 require six multipliers and four adders, the complexity is decreased. The data controller 2 formed of delay devices installed between the lattices 19 and 20 requires eight delay units. In addition, the data form converter or the data storing unit 21 which are used for processing the data that the output x(n) is fed back to the input side require six delay units.
Even when the above-described lattice structure is adapted, whenever the resolution level is increased by one level, the number of the delay units is exponentially increased, so that the chip area is increased when implementing the lattice structure using the integrated circuit. As shown in FIG. 2, it is not easy to design the system because there is not a scalable characteristic.
Accordingly, it is an object of the present invention to provide a discrete wavelet transform apparatus for a lattice structure which is capable of simplifying the hardware structure and implementing a scalable characteristic with respect to the different resolution levels and different filter lengths.
To achieve the above-objects, there is provided a discrete wavelet transform apparatus for a lattice structure which includes:
first through M-th lattice lattices installed in series along the length of a selected filter and each having an upper signal path and a lower signal path for supplying an output of the discrete wavelet transform apparatus;
a data form transform unit for converting the form of the input signal and supplying to the first lattice stage; and
wherein said data form transform unit, which receives an output of the upper signal path of the M-th lattice stage that the time tj(l) for receiving an allocation of a certain level among the resolution levels j is 2j*l+2jxe2x88x921xe2x88x921. Note that this formula, and in a similar manner, formulas 1, 2a, 2b, 3b discussed below, and the formula in FIG. 6, can also be written as (2j)(l+2xe2x88x921)xe2x88x921, with l replaced with 1 where appropriate. 2j*l+2jxe2x88x921xe2x88x921 has the following relationship, wherein X represents an input of the data form transform unit, u(n) represents an input of the discrete wavelet transform(DWT), Y represents an output of the M-th lattice stage, n represents a discrete time, l represents a certain number, U represents an upper signal path, and L represents a lower signal path:
XU0(n)=u(n) n=2I
=YUMxe2x88x921(nxe2x88x922jxe2x88x921), n=2j*1+2jxe2x88x921
XL0(n)=u(nxe2x88x921) n=2I
=YUMxe2x88x921(nxe2x88x922jxe2x88x921xe2x88x922jxe2x88x922), n=2j*1+2jxe2x88x921xe2x88x921
xe2x80x83and includes a variable maintaining unit and signal selection unit which satisfy the above-described formulas, and
when the time for receiving an allocation of a certain level among the resolution levels j is tj(l)=2j*l+2jxe2x88x921xe2x88x921, the input and output of the delay control unit includes the following relationship, wherein x represents an input and Y represents an output,
xe2x80x83xUi(n)=YUixe2x88x921(n)
XLi(n)=YLixe2x88x921(nxe2x88x922j), n=2j*1+2jxe2x88x921xe2x88x921,
xe2x80x83and a variable maintaining unit and signal selection unit which satisfy the above-described formulas are further provided.
Additional advantages, objects and features of the invention will become more apparent from the description which follows.